In, for example, hard disk drive (HDD) data storage systems, a continuous readback signal needs to be sampled prior to data detection. Data storage systems, however, introduce time-varying timing disturbances into the continuous readback signal. These delays are due to many factors, including disk speed variation, frequency offset between the different clocks used in the writing and reading processes, and clock wander. As data storage densities are pushed toward one terabit per square inch (1 Tb/in2) and beyond, advanced signal detection algorithms such as iterative soft decoding are being suggested to cope with the lower signal-to-noise ratios (SNRs) and higher inter-symbol interference (ISI) inevitable at these densities.
In HDD systems, low SNR is a direct consequence of decreased track widths of the recording medium to accommodate increased track density. Unfortunately, at low SNRs, conventional phase-locked loop (PLL)-based decision-directed timing recovery schemes exhibit a large residual timing jitter. Residual timing jitter refers to the residual timing error introduced by the timing recovery system and is the difference between the estimated timing disturbance and the actual timing disturbance in a continuous readback signal as it is processed by the timing recovery system. Large residual timing jitter leads to frequent loss of lock, an event where the estimated timing disturbance differs considerably from the actual timing disturbance for a significantly long duration leading to misindexing of the detected bits and thus error bursts. Large residual timing jitter erodes SNR gains achieved by advanced signal detectors and ensures loss of lock. It is therefore desirable to develop timing recovery methods and systems that can perform well in low SNR environments. For conventional PLL-based decision-directed timing recovery schemes, the residual timing jitter can be decreased by employing reliable detection schemes within PLLs, such as a full Viterbi structure with a long decision window instead of a Viterbi detector having a short decision window. It is difficult, however, to maintain the stability of a PLL having a long delay. Another approach for reducing residual timing jitter is to use a soft timing error detector (TED), which uses soft information from a Soft Output Viterbi Algorithm (SOVA) with a forced short decision window. Test results show that the soft TED provides some improvement in terms of the residual timing jitter and the overall bit error rate (BER). Nevertheless, the soft TED method alone may not provide adequate performance at low SNRs, especially when a large PLL bandwidth is needed to track a relatively rapidly changing timing disturbance.
Accordingly, there exists a need for a new timing recovery system and method to perform timing recovery in low SNR partial response recording channels.